Toward Structurally Safe Design-for-Trust Techniques

The globalized landscape of IC manufacturing has made intellectual property (IP) vulnerable to various untrustworthy entities, making security a crucial concern in circuit design. To safeguard IP confidentiality throughout IC manufacturing stages various Design-For-Trust (DFT) techniques like layout camouflaging, split manufacturing, and logic locking have been proposed. These techniques share a common objective: to obscure the true functionality of certain parts of the circuit’s netlist by obfuscating substructures, ensuring that even full access to the netlist does not enable successful reverse engineering. Although initially promising, these techniques have faced scrutiny due to the development of various attacks that challenge their utility.In this work, we analyze structural attacks, the most recent class of threats against DFT techniques that can reverse engineer the circuit by accessing only the protected netlist and searching for structural leakages in the protective mechanisms. We demonstrate that these leakages stem from security-agnostic synthesis tools, which prioritize power, area, and performance without considering security. Since attackers can employ various synthesis tools when targeting a circuit, merely providing a securityaware synthesis tool is insufficient for full protection. Therefore, we analyze various structurally safe obfuscation schemes and suggest security guidelines to hinder structural attacks, even when attackers utilize diverse synthesis tools.