A Design of PUF Circuit Using Adiabatic Logic

Physically Unclonable Functions (PUF) circuit is a circuit technology that uses variations in each parameter of an integrated circuit to identify the chips. This PUF circuit makes it possible to identify individual integrated circuits, making it possible to prevent the circulation of counterfeit circuits. Some silicon-based PUF circuits have been proposed, including a PUF circuit called QUALPUF and a low-power two-phase clocking adiabatic PUF circuit. In this paper, we designed an adiabatic SRAM-based circuit using a $0.18 \mu \mathrm{~m}$ CMOS process, which consumes less power than conventional PUFs, and has good uniqueness and reliability. In SPICE simulation, the energy consumption per $1 \mathrm{bit/cycle}$ of the proposed circuit is $\mathbf{1 3. 8 8}$ $\mathrm{fJ} / \mathrm{bit} / \mathrm{cycle}$, and the uniqueness and reliability values when the PUF circuit is connected in 4-bit cascode are $\mathbf{5 0. 0 7} \%$ and $\mathbf{9 9. 5 1} \%$, respectively.

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Publication Details

Published
2024-11-07
DOI
https://doi.org/10.1109/apccas62602.2024.10808900
Primary Topic
Integrated Circuits and Semiconductor Failure Analysis
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article
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article

A Design of PUF Circuit Using Adiabatic Logic

Yasuhiro Takahashi, Shoma Nagata
Integrated Circuits and Semiconductor Failure Analysis
article

A Design of PUF Circuit Using Adiabatic Logic

Yasuhiro Takahashi, Shoma Nagata
article en

Abstract

Physically Unclonable Functions (PUF) circuit is a circuit technology that uses variations in each parameter of an integrated circuit to identify the chips. This PUF circuit makes it possible to identify individual integrated circuits, making it possible to prevent the circulation of counterfeit circuits. Some silicon-based PUF circuits have been proposed, including a PUF circuit called QUALPUF and a low-power two-phase clocking adiabatic PUF circuit. In this paper, we designed an adiabatic SRAM-based circuit using a $0.18 \mu \mathrm{~m}$ CMOS process, which consumes less power than conventional PUFs, and has good uniqueness and reliability. In SPICE simulation, the energy consumption per $1 \mathrm{bit/cycle}$ of the proposed circuit is $\mathbf{1 3. 8 8}$ $\mathrm{fJ} / \mathrm{bit} / \mathrm{cycle}$, and the uniqueness and reliability values when the PUF circuit is connected in 4-bit cascode are $\mathbf{5 0. 0 7} \%$ and $\mathbf{9 9. 5 1} \%$, respectively.

Gifu University (JP)
Affordable and clean energy
Openalex Percentile: Top 78%
Integrated Circuits and Semiconductor Failure Analysis
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A Design of PUF Circuit Using Adiabatic Logic — Yasuhiro Takahashi, Shoma Nagata · (2024) | TGRS Research Map | TGRS