An On-chip High-resolution Delay Measurement Scheme for TSVs in 3DIC

This paper presents an on-chip high-resolution delay measurement scheme for the through silicon vias (TSVs) of 3DIC. Unlike previous TSV delay measurement schemes that tend to include some logic gates in the delay measurement results and hence the resolution is often in the range of hundreds of pico-seconds, we develop a novel ring-oscillaor measurement scheme that can systematically cancel out all gate delays and leave only the routing delays of TSVs. Experimental results on the TSMC 40 nm process technology show that we can achieve the resolution of a few picoseconds for TSV delay measurement, and the maximum error between our method and SPICE simulation is only 0.19 ps even with process variation considered, which demonstrates the high resolution and high accuracy of our method.