A Novel Standard Cell Layout Methodology for Low Power IOT Applications

As the size of MOS transistors decreases to sub100 nm nodes, leakage currents are increasingly becoming a significant factor in power consumption. The leakage contribution of standard cells, which are the basic components of chip designs, is exceptionally high. The conventional methods of optimizing these standard cells at the architecture level are no longer sufficient to ensure the demanding requirement of extended battery life for advanced applications such as Internet of Things (IoT), without sacrificing the chip’s size or operating frequency. Additional optimizations at the standard cell layout level are required in order to develop a power-efficient solution that is suitable for IoT applications. We present a novel method for standard cell layout design that transitions from the conventional metal-based routing technique to a metaldiffusion based routing approach. We utilize the inverse narrow width effect (INWE) to determine the optimal transistor width for achieving both low power consumption and fast operational speed. Subsequently, the layouts are designed after considering the device level analysis to minimize the total power usage without compromising the area and operating frequency of our design. The synthesis of a DMA controller demonstrates that by employing our proposed technique of utilizing low power standard cells, we can obtain a 14% decrease in leakage power without any negative impact on the operating frequency and area of the design.