A 348-nW, 10.5-bit Analog Front End with Amplifier Resistor Series Loop for Acoustic Application

This paper presents a low-power, wide bandwidth analog front end (AFE) for acoustic sensing integrated with the function of sound amplification and digitization. An amplifier resistor series loop (ARSL) is used to set the optimal input bias. To improve linearity and reduce leakage, this paper proposes a bootstrap based on a transmission gate. The dynamic comparator adopts a dynamically powered preamplifier stage, providing high accuracy while ensuring low power consumption. The analog front end is implemented in a standard $0.18 \mu \mathrm{~m}$ CMOS process, and 348 nW was consumed. A variable gain of 14-32.7 dB, bandwidth range of $5.1 \mathrm{~Hz}-16.5 \mathrm{KHz}$, effective number of bits (ENOB) in 10.5 bits, and 7.1 fJ/conversion step are achieved in the AFE we present.