A Radiation-Hardened Serial Peripheral Interface with an ECC-Protected SRAM in a 65nm CMOS Technology

Benefiting from a reduction in rocket launch costs and an increase in market scale, low earth orbit (LEO) satellites have become a new focus in the field of technology in recent years. Their characteristics of low latency, high bandwidth and low cost provide advantages for mobile communication. Related applications, such as phased array antennas and beamforming ICs, have also been developed accordingly. However, the space environment is filled with a large number of cosmic rays, and these high-energy radiation particles may cause soft errors in ICs. Therefore, mitigating the impact of radiation will be a major challenge. This work proposes a radiation-hardened serial peripheral interface (SPI) and an SRAM with error-correcting code (ECC) protection for application in LEO satellites. By analyzing through a mathematical bit error rate model and relevant information about SRAM, a suitable ECC is selected. Additionally, radiation-hardened cells are incorporated into the SPI.