A 14.6-ENOB Second-Order Noise-Shaping SAR ADC With kT/C Noise Shifting

Oriented at achieving high resolution and power efficiency, the noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) is a popular architecture. Although the thriving NS-SAR ADC can shape the quantization error, the loop filters do not contribute to suppressing noise during sampling, which is usually settled by utilizing large capacitors. This paper presents a second-order NS-SAR ADC with kT/C noise shifting, which exploits the errorfeedback (EF) structure to realize aggressive noise-shaping and substantially reduces the input capacitor size without the large kT/C noise penalty. Implemented in $180-\mathrm{nm}$ CMOS, this work achieves 91-dB signal-to-noise ratio (SNR) and 89.5-dB signal-to-noise-distortion ratio (SNDR) with $417-\mathrm{kHz}$ bandwidth (BW). It uses merely 0.246 -pF input capacitance, which is $6.5 x$ smaller than prior NS-SAR ADCs with similar oversampling ratio (OSR) and SNDR.