A 500MHz, 0.5% THD With 400mVpp Linear Transimpedance Amplifier (TIA) for Analog Optical and In-memory Computing Applications

As Moore’s Law gradually reaches its limit, the current traditional chip architecture is limited by the physical size of electronic transistors approaching the speed bottleneck. Optoelectronic computing, with its ultra-high parallelism and speed, is considered to be one of the most powerful competitive solutions for disruptive computing architectures in the future. Furthermore, RRAM-based compute-in-memory (CIM), as a computing system with non-von Neumann architecture, has been reported as one of the most promising neural network accelerators in the future. Among them, a linear transimpedance amplifier (TIA) is considered to be a key circuit for realizing current-to-voltage conversion and has extremely high requirements for its linearity. The proposed TIA employs an inverter-based transimpedance front-end (TFE) to realize the conversion from current to voltage. At the same time, the classAB stage is applied to the gain stage to achieve a trade-off between high swing and high linearity. Implemented in the 28 $\mathbf{n m}$ CMOS process, the proposed TIA supports 500 MHz bandwidth with a DC transimpedance gain of $74 \mathrm{~dB} \Omega$ and the total harmonic distortion (THD) is less than $\mathbf{0. 5 \%}$ for an output swing of 400 mVpp.