3D Digital Compute-in-Memory Benchmark with A5 CFET Technology

Digital compute-in-memory (DCIM) has recently emerged as a promising solution to address the scalability and accuracy challenges in analog CIM (ACIM) for next-generation AI hardware acceleration. In this work, we present a 3D DCIM accelerator design implemented at 5 Angstrom (A5) Complementary FET (CFET) technology node. A novel compact 8T CFET-based DCIM bit cell (6T SRAM+2T AND gate) is proposed over the conventional 10T DCIM bit cell, and its functionality is verified through TCAD simulation. Furthermore, macro-level and system-level power, performance, and area (PPA) performance of the proposed design is evaluated using NeuroSim V1.4, a CIM benchmark framework for leading-edge technology nodes. It was shown that A5 DCIM can achieve approximately 70% higher Figure of merit (FOM) compared to state-of-the-art 1nm DCIM design. Our findings suggest continued scaling benefits by employing CFET technology for the DCIM design.