A 1.3 nW, 0.014 %/V and Dual-output CMOS Voltage Reference with Self-biased Current Source

A nano-watt CMOS-only and dual-output voltage reference is presented for ultra-low power applications. The chip was fabricated in a standard $0.18-\mu \mathrm{m}$ CMOS process. To reduce area and improve energy efficiency, an active load is used to obtain two reference voltages in a single current branch. By utilizing the significant $\Delta \mathbf{V}_{\text {TH }}$ between native NMOS transistor and standard NMOS transistor, a self-biased current source was designed, reducing power consumption to 1.3 nW. To reduce the dependence of bias current on the supply voltage, a pre-stabilized circuit based on a voltage regulator and a leakage-isolated source follower is presented. Based on the 5-chip measurement results, the average TCs of $\mathrm{V}_{\text {REF1 }}$ and $\mathrm{V}_{\text {REF } 2}$ are $36.67 \mathrm{ppm} /{ }^{\circ} \mathrm{C}$ and 128.55 $\mathbf{p p m} /{ }^{\circ} \mathrm{C}$, respectively, in a temperature range from $-30{ }^{\circ} \mathrm{C}$ to 100 °C without trimming. The line sensitivity of $\mathrm{V}_{\mathrm{REF} 1}$ is $\mathbf{0. 1 1 6} \% / \mathrm{V}$ when the $\mathrm{V}_{\mathrm{DD}}$ supply varies from 1.05 V to 1.8 V, and the line sensitivity of $\mathrm{V}_{\mathrm{REF} 2}$ is $0.014 \% / \mathrm{V}$ with 0.65 V to 1.8 V supply. The average PSRR with 1.05 V supply are $-55 \mathrm{~dB},-63 \mathrm{~dB}$ at 10 $\mathrm{Hz},-43 \mathrm{~dB},-38 \mathrm{~dB}$ at 100 Hz and $-55 \mathrm{~dB},-70 \mathrm{~dB}$ at 1 MHz, respectively.