High-Level Synthesis of FPGA-Based Chirp Match Filtering for Synthetic Aperture Radar Systems

This paper presents the implementation of chirp match filtering for Synthetic Aperture Radar (SAR) on a field-programmable gate array (FPGA) using High-Level Synthesis (HLS). HLS enables higher productivity by significantly reducing development time compared to traditional hardware description languages (HDL). A C-based programming approach is employed to leverage parallel processing, which is critical for high-performance signal processing tasks. The design utilizes a symmetric chirp signal as the reference for match filtering, with optimizations implemented through parallelism in the filtering process. Experimental results show that the FPGA-based match filtering, programmed using HLS, achieves low latency and high performance, with a speed increase of 937 times compared to running the same process in Octave on a standard computer.

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Published
2024-11-12
DOI
https://doi.org/10.1109/icramet62801.2024.10809195
Primary Topic
Advanced SAR Imaging Techniques
Type
article
Field-Weighted Citation Impact
0.00

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article

High-Level Synthesis of FPGA-Based Chirp Match Filtering for Synthetic Aperture Radar Systems

Agus Hendra Wahyudi, Agus Wiyono, Effendi Dodi Arisandi, Satria Arief Aditya et al.
Advanced SAR Imaging Techniques
article

High-Level Synthesis of FPGA-Based Chirp Match Filtering for Synthetic Aperture Radar Systems

Agus Hendra Wahyudi, Agus Wiyono, Effendi Dodi Arisandi, Satria Arief Aditya, Andria Arisal, Farohaji Kurniawan, Iman Firmansyah, Bambang Setiadi, Abdurrasyid Ruhiyat, Jefri Abner, Abdul Rohman, Nurul Chasanah
article en

Abstract

This paper presents the implementation of chirp match filtering for Synthetic Aperture Radar (SAR) on a field-programmable gate array (FPGA) using High-Level Synthesis (HLS). HLS enables higher productivity by significantly reducing development time compared to traditional hardware description languages (HDL). A C-based programming approach is employed to leverage parallel processing, which is critical for high-performance signal processing tasks. The design utilizes a symmetric chirp signal as the reference for match filtering, with optimizations implemented through parallelism in the filtering process. Experimental results show that the FPGA-based match filtering, programmed using HLS, achieves low latency and high performance, with a speed increase of 937 times compared to running the same process in Octave on a standard computer.

Indonesian National Institute of Aeronautics and Space (ID), National Nuclear Energy Agency of Indonesia (ID), National Research and Innovation Agency (ID)
Lembaga Pengelola Dana Pendidikan
Affordable and clean energy
Openalex Percentile: Top 59%
Advanced SAR Imaging Techniques
DOISourceOpenAlex
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High-Level Synthesis of FPGA-Based Chirp Match Filtering for Synthetic Aperture Radar Systems — Agus Hendra Wahyudi, Agus Wiyono, et al. · (2024) | TGRS Research Map | TGRS