A 14b Calibration-Free Pipelined SAR ADC Using a Single-Stage Gain Boost FIA

This paper presents a calibration-free pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with a single-stage gain boost cascoded floating inverting amplifier (FIA). The open-loop gain of the cascoded FIA is increased by 28 dB through a gain boost bias technique, achieving an accurate 32-fold inter-stage gain. The proposed cascoded dynamic amplifier also offers stable linear amplification and low noise. The prototype ADC is fabricated using 65 nm process technology and achieves an SNDR of 83.73 dB at $10 \mathrm{MS} / \mathrm{s}$ without calibration of inter-stage gain. The proposed amplifier consumes only 83.89 uA from a $1.2-\mathrm{V}$ supply, leading to a Schreier figure-of-merit(FoM) of $\mathrm{1 8 4 . 2 1 ~ d B}$.