Global Routing Optimization Analysis based on Deep Reinforcement Learning

Integrated Circuit (IC) design is a multi-stage and complex process, with each stage from requirements analysis to final manufacturing presenting its unique challenges. As technology and market demands evolve, the complexity and difficulty of IC design continue to increase, necessitating more robust automated design systems to assist engineers in overcoming these challenges. This paper focuses on global routing, a critical step in IC design responsible for determining the approximate paths of signal lines on a chip to optimize resource allocation, signal integrity, and power control. Global routing has always been a challenging aspect of IC physical design. Common solutions primarily rely on heuristic-driven greedy methods, which have strict limitations. We aim to find better solutions to minimize total wire length (WL) and edge overflow (OF). This paper references an IC global routing method based on Deep Reinforcement Learning (DRL) and improves the traditional Deep Q-Network (DQN) algorithm to a Double Deep Q-Network (DDQN) to address issues in IC global routing. The method aims to use DDQN to enhance the stability and performance of DQN in handling complex routing problems. Experimental results compare DDQN with the commonly used $A^{*}$ search algorithm, demonstrating the optimized performance of DDQN in global routing tasks, especially in partially edge-exhausted problems, where DDQN excels and successfully optimizes total wire length.