An Eight-Channel Analog Front-End Circuitry for the Application of Neural Signal Sensing

This paper presents an eight-channel analog frontend (AFE) circuit designed to monitor neural activities to assess pharmaceutical efficacy before and after drug administration for multiple system atrophy (MSA). Each sensing channel includes a low-noise amplifier (LNA), the input stage of a programmable gain amplifier (PGA). All the channels share the output stage of PGA, an analog-to-digital converter (ADC) input driver, and a successive-approximation register (SAR) ADC to save area and power consumption. A serial-to-peripheral interface (SPI) circuit is employed to adjust circuit parameters and configure the signal chain. A prototype chip, designed and fabricated in a $0.18 \mu \mathrm{~m}$ CMOS process occupies an area of $11.5, \mathrm{~mm}^{2}$. The designed LNA achieves a noise efficiency factor of 1.94. The designed PGA consumes $3.78 \mu \mathrm{~W}$ power and attains a total harmonic distortion (THD) of -74.3 dB with $640 \mathrm{mV}_{\mathrm{pp}}$ output swing. With a 0.1% THD requirement, the allowable output signal magnitude of the developed AFE circuitry is $1.16 V_{\mathrm{pp}}$.

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Publication Details

Published
2024-11-07
DOI
https://doi.org/10.1109/apccas62602.2024.10808553
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
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article

An Eight-Channel Analog Front-End Circuitry for the Application of Neural Signal Sensing

Yiwei Peng, Zu-Jia Lo, Sheng-Yu Peng, Ming-Hsien Tsai
Analog and Mixed-Signal Circuit Design
article

An Eight-Channel Analog Front-End Circuitry for the Application of Neural Signal Sensing

Yiwei Peng, Zu-Jia Lo, Sheng-Yu Peng, Ming-Hsien Tsai
article en

Abstract

This paper presents an eight-channel analog frontend (AFE) circuit designed to monitor neural activities to assess pharmaceutical efficacy before and after drug administration for multiple system atrophy (MSA). Each sensing channel includes a low-noise amplifier (LNA), the input stage of a programmable gain amplifier (PGA). All the channels share the output stage of PGA, an analog-to-digital converter (ADC) input driver, and a successive-approximation register (SAR) ADC to save area and power consumption. A serial-to-peripheral interface (SPI) circuit is employed to adjust circuit parameters and configure the signal chain. A prototype chip, designed and fabricated in a $0.18 \mu \mathrm{~m}$ CMOS process occupies an area of $11.5, \mathrm{~mm}^{2}$. The designed LNA achieves a noise efficiency factor of 1.94. The designed PGA consumes $3.78 \mu \mathrm{~W}$ power and attains a total harmonic distortion (THD) of -74.3 dB with $640 \mathrm{mV}_{\mathrm{pp}}$ output swing. With a 0.1% THD requirement, the allowable output signal magnitude of the developed AFE circuitry is $1.16 V_{\mathrm{pp}}$.

National Taiwan University of Science and Technology (TW)
Affordable and clean energy
Openalex Percentile: Top 77%
Analog and Mixed-Signal Circuit Design
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