Optimizing Computational Efficiency: A Novel Approach through XOR-logic Operation in In-Memory Computing

Currently, with the technology progress, numerous AI applications are generated, including those AI applications for smart living, smart city, smart agriculture, etc. However, the architecture of modern computers remains the Von-Neumann architecture. The extensive data movement between the CPU and memory incurs the Von-Neumann bottleneck, leading to significant power consumption and increased latency. In-Memory Computing which implements basic logic and arithmetic operations within the memory to enhance computational efficiency is an effective method to mitigate the performance loss in the Von-Neumann bottleneck. In this paper, we propose a novel in-memory computing architecture with multi-logic operation. By using different control signals, the 8+ T static random-access memory (SRAM) architecture not only generates basic logic operations values simultaneously but also, through the control of pass transistor logics, yields the computational results of adders or subtractors. The experimental results show the feasibility of the proposed architecture. Furthermore, compared to conventional design, the proposed architecture demonstrates a 43.9% reduction in power-delay product.