A 10-MS/s Binary Weight-merged SAR ADC for Real-Time Health-Monitoring System Applications

This paper presents a successive approximation registers analog-to-digital converter (SAR ADC) that combines the binary relationship of the values of multiplication and accumulation (MAC) of computing in memory (CIM) into the resolution of SAR ADC. To satisfy the requirements of edge computing, this proposed architecture can not only save the power consumption from digital circuits and data converters by about 33% but also improve the area efficiency of the circuit by reusing the capacitor array of SAR ADC, making this architecture more beneficial for the low power design on a system overview. Simulation results show that this proposed ADC operating at $10 \mathrm{MS} / \mathrm{s}$ can achieve a signal-to-noise and distortion ratio (SNDR) of 47.41 dB while occupying $\sim 1 \mathrm{~mm}^{2}$ and consuming $133.84 \mu \mathrm{W}$ under 1.2 V and 1 V power supply voltage, respectively, which achieves high energy efficiency and accuracy for the edge health-detecting applications.