Radiation-hardened Configuration Registers with SPI Interface Protocol in a 65nm CMOS Technology

With the recent growth in low earth orbit satellites and its advantages of low transmission latency, soft errors in integrated circuits due to radiation have garnered attention and discussion. Compared to traditional methods that apply radiation hardness by process, using radiation hardness by design has become a new methodology today. This paper begins by reviewing previous works’ proposed radiationresistant circuit designs and analyzing their SEU protection. Then, we select one design from among them as the component in on-chip registers. Moreover, a specific cell-based design flow will be introduced and applied to the radiation-hardened chip. The chip comprises configuration registers and employs a serial peripheral interface for communication with a 65 nm CMOS technology.