A Second-Order Noise Shaping SAR ADC with Fully Passive Integrators and Pole Optimization

This article proposes a new second-order noise-shaping architecture for successive approximation register (SAR) analog-to-digital converters (ADCs), which is a hybrid scheme with capacitor stacking and a multi-input comparator to achieve enough gain in the transfer function. Instead of high-gain comparators and three-path comparators, a two-path multi-input comparator is used in this architecture, which reduces the noise contribution and power consumption. A second-order noise transfer function (NTF) with two zeros at $(0.8,0)$ and a negative pole at $(-0.8,0)$ is also implemented, resulting in a better noiseshaping ability compared to the traditional NTF of second-order noise-shaping. This design is fabricated in TSMC 180 nm technology, and the simulation results reveal that the proposed noise-shaping SAR ADC can achieve a signal-to-noise and distortion ratio (SNDR) of $\mathbf{7 4. 1 5} \mathbf{d B}$ in the bandwidth of $\mathbf{1 2 5} \mathbf{~ k H z}$. The Schreier figure of merit (FoM) and Walden FoM are 161 dB and 248 fJ/conv.-step.