Influences of Adjacent High Voltage on the Characteristics and Reliability of SOI Power Devices for Automotive Application

Silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) technologies based on the 0.18-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m process node are popular for automotive applications due to their superior features. In the practical ICs, the devices are usually arranged tightly to balance the performance and chip area. As for the p-type lateral double-diffused MOS (pLDMOS), the drain and source are both applied on the high voltage whatever the layout configuration is. In this way, if the power devices are adjacent to the pLDMOS, the high voltage applied on the pLDMOS will result in unpredictable influences on their features. In this work, the influence of this adjacent high voltage on the power devices, including n-type lateral double-diffused MOS (nLDMOS), lateral insulated-gate bipolar transistor (LIGBT), pLDMOS with source inside configuration, and pLDMOS with drain inside configuration, has been comprehensively investigated both at room temperature (25 ° C) and high temperature (175 ° C) for the automotive application. It is found that the nLDMOS and LIGBT are not influenced by the adjacent high voltage both at 25 ° C and 175 ° C except for the hot-carrier degradation. Meanwhile, the pLDMOS with drain inside configuration is also not affected except for the off-state breakdown voltage. However, the pLDMOS with source inside configuration is severely influenced by the adjacent high voltage both at 25 ° C and 175 ° C, including off-state breakdown voltage, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I} _{\text {DS}}$ </tex-math></inline-formula>–<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {DS}}$ </tex-math></inline-formula> curves, hot-carrier degradation, and ESD robustness. The inner reasons are analyzed and discussed in detail with the technology computer-aided design (TCAD) simulators. Based on the pLDMOS device, a proposed double deep trench isolation (DTI) structure with P+ contact is fabricated, which effectively suppresses the influences of adjacent high voltage.