Integrating 3T-DRAM Into 1T Layout With Substrate Bipolar Effect Using 22 nm FDSOI Technology

A novel device integrating all the functions of the three-transistor Dynamic Random Access Memory (3T-DRAM) into one-transistor (1T) layout is demonstrated with 22 nm fully depleted silicon-on-insulator (FDSOI) technology. The 1T layout is realized by the proposed bipolar junction transistor (BJT) assisted in-situ sensing DRAM (BIS-DRAM), in which the erase and program function are conducted through a BJT embedded in the substrate. The charge is stored in the buried oxide (BOX) capacitor of the SOI MOSFET and read out through the interface coupling effect, with the top gate serving as a selector for random access. This smart design enables the non-destructive and in-situ reading with low disturbance and compact layout. Experimental results demonstrate 5 ns write speed and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\ge 7.9$ </tex-math></inline-formula> s retention time, with a minimum write voltage down to 0.2 V, showing great potential for embedded DRAM (eDRAM) applications.