Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs

The application of artificial intelligence (AI) requires advanced computation to address complex problems. However, the improvement of binary computing systems supporting these applications is approaching their limits due to atomic-level scaling. Regarding this challenging situation, ternary computing is gaining more attention due to its better data saving/computing/moving capability. Thus, ternary logic based on various devices was proposed, but these circuits are still encountering issues of high-power consumption, low operating speed, and challenges in manufacturing compared to silicon-based circuits. Therefore, this paper presents a methodology for designing ternary logic based on Depletion-mode metal-oxide-semiconductor field-effect transistor (DEPFET) and multi-threshold voltage complementary metal-oxide–semiconductor (MTCMOS). Our silicon-based devices are easier to manufacture and support high-speed/low-power operations through our complementary ternary logic. Our balanced ternary full adder (BTFA) is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9.70\times $ </tex-math></inline-formula> better energy efficiency than the latestcarbon nanotube field-effect transistor (CNTFET) based BTFA. We also propose the first methodology to design a ternary cell layout in multi-height standard cell design. We propose an algorithm for the best ternary cell layout and a concept of integrated layout that reduces area when required cells are close to each other.