A 13.2-fJ/Step 74.3-dB SNDR Pipelined Noise-Shaping SAR+VCO ADC

This work presents an OTA-free pipelined passive noise-shaping successive approximation register (NS-SAR) + VCO ADC that offers high resolution (>12-bit) with only a 5-bit NS-SAR stage and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula>–<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$36\times $ </tex-math></inline-formula> lower sampling capacitor compared to state-of-the-art NS-SARs with similar ENOB. Pipelining the NS-SAR and VCO stage linearizes VCO by reducing its input swing, increases the VCO integration time and its energy efficiency, and improves the SFDR of ADC by suppressing frequency dependency of interstage gain. We demonstrate a simple calibration technique to extract interstage gain and track VCO gain accurately in the background. Fabricated in 65-nm CMOS, the prototype ADC achieves the best Walden FoM among state-of-the-art passive NS-SAR ADCs in similar technology and consumes 0.12 mW with SNDR/SFDR of 74.3/89.1 dB at 13.2 fJ/step for OSR of 9.