Design and Evaluation of High-Speed Approximate Multipliers Based on Improved Error Distance 4:2 Compressors for Error Resilient Image Applications

Approximate Computing (AC) have widely adopted in designing large-scale logic circuits.In particular, approximate adder and multiplier circuits have been considerably targeted in the realm of image processing due to their high energy-saving while preserving proper level of computing accuracy.Nevertheless, intensive research and development are maintained in the means of seeking more matured designs that effectively prioritize design overheads over error resilience.In this paper, low error-distance approximate 4:2 compressor circuits are proposed to construct high-speed approximate adders.The developed compressors realize high logic computing and incur competitive area and power consumption, and therefore, they were leveraged to configure an approximate 88 multiplier designs.To achieve a favorable trade-off between computational accuracy and hardware resource usage, we develop a simulation framework that evaluates the accuracy of the proposed multiplier designs at the gate-level (measuring error distance) and at the application-level (evaluating SNR and SSIM) of an image.The framework truncates specific propagated carry bits, i.e., least significant bits (LSBs), to realize profitable area-and power-saving.Furthermore, two main high-speed multiplier designs are proposed herein, namely High Computing Performance Approximate Multiplier (HCP-AMUL) and HCP Low Error Approximate Multiplier (HCPLE-AMUL).Matlab R2022b along with VS Code are used for running simulations and accuracy evaluation, while Vivado 2018.2 is utilized for HDL reconfigurable logic design and implementation and evaluation of area, power, and speed, configured on an FPGA Xilinx Nexys 4 Artix-7 (XC7A100T-1CSG324) trainer board.The experimental results demonstrate the efficacy of the developed multipliers as the developed HCPLE-AMUL delivers 54.26%, 11.72%, and 449.85 of speedup, power saving, and Power-Delay-Area-Error-Product (PDAEP) improvement, respectively.On the other hand, the presented HCP-AMUL realizes an improved saving of area and power at the expense of an acceptable lowering of computation accuracy.It achieves 9.66%, 505.40, and 53.73% of power saving, PDAEP, and speedup respectively, Thus, the proposed compressor and multiplier circuits potentially can be promising approximate computing modules for image processing applications to provide improved trade-off between computation accuracy and logic utilization complexity.