A 9.14 μW, 66.67 MHz 4-Bit Bi-Directional Shift Register Using GDI-Based JK Flip Flop

This paper undertakes a comprehensive comparative analysis of Serial-in-Parallel-out (SIPO) shift register design employing master-slave JK flip-flops constructed through three distinct techniques: Gate Diffusion Input (GDI), Transmission Gate, and Complementary Metal-Oxide-Semiconductor (CMOS). Each technology's design process and key parameters are thoroughly investigated and compared, focusing on critical metrics such as propagation delay, power consumption, slew rate, frequency, and duty cycle. The proposed GDI-based master-slave flip-flop design has successfully shown 64.52% and 77.28% less power consumption than transmission gate and CMOS technology, respectively. The study extends its analysis by contrasting the performance of the SIPO shift register resulting in 22.58 ns and 4.552 nJ power-delay product. Results demonstrate the comparative advantages of offering valuable guidance for designers in selecting the most suitable approach for SIPO shift register implementations.