Novel Architecture of a Low Power D Flip-Flop Based Compact Frequency Divider for Wideband PLL Applications

In this study, a 90nm CMOS frequency divider utilizing D-type flip-flop integrated with a buffer circuit for enhanced performance at low voltage is introduced. The divider covers a wide frequency range from 2.496 GHz to 9.992 GHz, providing a tuning range of 120%. It operates efficiently within a low voltage range of 0 to 0.8 V, achieving optimized performance at 0.8 V. The power consumption varies from <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{0.02325}\ \mu \mathbf{W}$</tex> to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{15.39}\ \mu \mathbf{W}$</tex>, with a notably low consumption of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{15.39}\ \mu \mathbf{W}$</tex> at 0.8 V. The proposed architecture exhibits favorable phase noise characteristics, achieving -138.3009 dBc/Hz at a 1 MHz offset frequency. To comprehensively evaluate the circuit's performance, the figure of merit (FOM) is calculated yielding values of -224.387 dBc/Hz or 7797.27 which demonstrates an exceptional balance between locking range and power dissipation. Also, the implemented divider occupies a compact area of only <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{0.0000054584}\ \mathbf{mm}^{\mathbf{2}}$</tex>. To assess the stability of the system across diverse environments, process corner and temperature sweep analysis is also conducted. To sum up, the proposed design effectively employs D-type flip-flops to achieve wide frequency range with minimal voltage, power consumption, and compact size suitable for various wireless communication applications.