A Comparative Analysis of 4-Bit Adder Architectures for Enhanced Efficiency in Conventional CMOS Technology

Throughout the years, with the miniaturization of VLSI technology, adders form an essential component of almost every contemporary integrated circuit. The prerequisite of an adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. The race to create the most optimized device structure is getting harder and faster, as more compact digital devices with the lowest power consumption keep coming out and replacing each other. The optimal adder architecture is crucial for modern digital systems to enhance performance. Hence, choosing a perfect architecture that is compact and has low power consumption can be done with conventional CMOS technology by rationally comparing the different types of adders based on various performance parameters. Among the vast realm of adders, this research paper analyzes five 4-bit adder architectures, namely Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA), Carry Select Adder (CSA), Carry Save Adder (CSaA), and lastly Carry Skip Adder (CSkA). The study evaluates performance metrics of adder architectures including transistor count, average power, area, frequency, and propagation delay using Cadence Virtuoso. This work shows that RCA has simplicity but a significant propagation delay. On the other hand, the CLA improves speed but uses increased area. Innovative carry-save techniques can help to mitigate delay. Considering all parameters, CSkA is the most efficient adder with the least transistor count of 182, area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{16880}\ \mu m^{2}$</tex>, and average power requirement of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{50.04}\ \mu \mathbf{Watt}$</tex>.