A 64×64 Gated-SPAD Image Sensor With 2-D and 3-D Imaging Using a Time-Domain Sampling Histogram

A proof-of-concept prototype is presented, which can be used for 2-D and 3-D imaging with a resolution of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$64\times 64$ </tex-math></inline-formula>, and it consists of a 110-nm complementary metal oxide semiconductor (CMOS) sensor chip, a gated high-voltage driver circuit, and an additional field-programmable gate array (FPGA) to perform the digital signal processing (DSP), and a laser driver circuit. The sensor chip consists single-photon avalanche diode (SPAD) array with a resolution of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$64\times 8$ </tex-math></inline-formula>, 512 passive quenching circuits, 64 time-to-digital converter (TDC) with 160-ps resolution and 80-ns dynamic range, and readout circuits. The gated high-voltage driver circuit is used to control the working time of the SPAD, which can improve background noise suppression capability, linearity of 2-D imaging, and extend the dynamic range of the sensor chip. The DSP contains the partial histograms based on time-domain sampling algorithm, the histogram-based 2-D imaging algorithm, the backpropagation (BP) neural network filter, and the nonlinear fitting algorithm. Compared with traditional partial histograms, partial histograms based on a time-domain sampling algorithm can further reduce the utilization of logical unit resources of the histogram and improve the signal-to-noise ratio (SNR) of coarse histograms. The proposed histogram-based 2-D imaging algorithm can improve linearity and reduce the in-pixel counter compared with traditional 2-D imaging technology. The extensive experiments show that measurement distance, measurement accuracy, and frame rate are 64 m, 20 cm, and 10 Hz at 2 klux, respectively. When the background light is increased to 100 klux, the effective measurement distance is reduced to 8 m. In 2-D imaging, SPAD receives more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 10^{6}$ </tex-math></inline-formula> photons/s without distortion.

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Publication Details

Journal
IEEE Transactions on Instrumentation and Measurement
Published
2024-12-25
DOI
https://doi.org/10.1109/tim.2024.3522619
Citations
3
Primary Topic
CCD and CMOS Imaging Sensors
Type
article
Field-Weighted Citation Impact
0.63

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article

A 64×64 Gated-SPAD Image Sensor With 2-D and 3-D Imaging Using a Time-Domain Sampling Histogram

Zhangming Zhu, Hao Shan Shi, Dong Li, Rui Ma
3 citations
IEEE Transactions on Instrumentation and Measurement
CCD and CMOS Imaging Sensors
0.63
article

A 64×64 Gated-SPAD Image Sensor With 2-D and 3-D Imaging Using a Time-Domain Sampling Histogram

Zhangming Zhu, Hao Shan Shi, Dong Li, Rui Ma
article en
3 citations

Abstract

A proof-of-concept prototype is presented, which can be used for 2-D and 3-D imaging with a resolution of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$64\times 64$ </tex-math></inline-formula>, and it consists of a 110-nm complementary metal oxide semiconductor (CMOS) sensor chip, a gated high-voltage driver circuit, and an additional field-programmable gate array (FPGA) to perform the digital signal processing (DSP), and a laser driver circuit. The sensor chip consists single-photon avalanche diode (SPAD) array with a resolution of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$64\times 8$ </tex-math></inline-formula>, 512 passive quenching circuits, 64 time-to-digital converter (TDC) with 160-ps resolution and 80-ns dynamic range, and readout circuits. The gated high-voltage driver circuit is used to control the working time of the SPAD, which can improve background noise suppression capability, linearity of 2-D imaging, and extend the dynamic range of the sensor chip. The DSP contains the partial histograms based on time-domain sampling algorithm, the histogram-based 2-D imaging algorithm, the backpropagation (BP) neural network filter, and the nonlinear fitting algorithm. Compared with traditional partial histograms, partial histograms based on a time-domain sampling algorithm can further reduce the utilization of logical unit resources of the histogram and improve the signal-to-noise ratio (SNR) of coarse histograms. The proposed histogram-based 2-D imaging algorithm can improve linearity and reduce the in-pixel counter compared with traditional 2-D imaging technology. The extensive experiments show that measurement distance, measurement accuracy, and frame rate are 64 m, 20 cm, and 10 Hz at 2 klux, respectively. When the background light is increased to 100 klux, the effective measurement distance is reduced to 8 m. In 2-D imaging, SPAD receives more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 10^{6}$ </tex-math></inline-formula> photons/s without distortion.

IEEE Transactions on Instrumentation and MeasurementVol. 74
Xidian University (CN)
National Natural Science Foundation of China, National Science and Technology Major Project, Fundamental Research Funds for the Central Universities
Affordable and clean energy
Openalex Percentile: Top 30%
CCD and CMOS Imaging Sensors
0.63
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