A 1.48-fs FoM Analog Capacitorless-LDO With Cascade-Inverter-Based Pseudo-Power Transistor

A capacitorless analog low-dropout regulator (CL-LDO) with cascade-inverter-based pseudo-power transistor is presented in this letter. The proposed architecture supports ultralow-voltage operation, fast transient response, high current efficiency, and high loop gain with low quiescent current along the full load range. The proposed CL-LDO can be easily implemented without any external transient-enhancement circuit. The circuit is fabricated in a 65-nm LP CMOS process with an active area of 0.00782 mm2. The minimum supply voltage can be as low as 0.5 V. The minimum dropout voltage is 20 mV. Under a 1-V supply, the undershoot voltage with 100-mV dropout voltage is 87 mV and settles down within 10 ns when the load current increases from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$100~\boldsymbol {\mu }$ </tex-math></inline-formula> A to 50 mA within 5-ns edge time. The measured quiescent current is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4~\boldsymbol {\mu }$ </tex-math></inline-formula> A. The transient figure of merit is 1.48 fs.