A Novel 4H-SiC Split-Gate CIMOSFET With Improved Electrical Performance Using N-Type Buried Layer

This work proposes a two-layer conductive split-gate MOSFET with step central implant (CI) region (TCSG-CIMOSFET), enhancing gate oxide reliability and reducing gate-drain capacitance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {gd}}\text {)}$ </tex-math></inline-formula>. The P-type step CI region serves to enhance device gate oxide reliability by mitigating the maximum oxide electric field (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {ox}}\text {)}$ </tex-math></inline-formula>. Due to the reducing of the gate-to-drain overlapped region, TCSG-CIMOSFET has a low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {gd}}$ </tex-math></inline-formula>. Furthermore, the technology of conductivity modulation is applied to TCSG-CIMOSFET, which increases channel carrier concentration to reduce the specific on-resistance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {on, {sp}}}\text {)}$ </tex-math></inline-formula>. In the TCAD simulation, the TCSG-CIMOSFET improves the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {ox}}$ </tex-math></inline-formula>, BFOM, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {gd}}$ </tex-math></inline-formula>, HF-FOM by 50%, 43%, 45%, 49%, respectively. The enhanced performance suggests that TCSG-CIMOSFET is an excellent choice for high efficiency and high frequency power electronic applications.