Proficient Quantum-Dot Cellular Automata Based XOR Gate Layout Generator for Image Processing Applications

The Conservative lithography-based VLSI technology has been able to increase processing power and achieve proportionate scaling in feature size. However, present work expose that deterioration of these devices (as a result of vital physical confines of CMOS technology) will head to undesirable consequences such as doping fluctuations, power dissipation, short channel effects and electro-migration failures. These repercussions will cause a decline in a number of parameters, including diffusion barriers, off-state leakage, gate depletion, switching performance, and stray capacitances. Furthermore, it is predicted that the 7 nm channel dimension will mark the conclusion of the CMOS technology’s growth process. In order to replace conventional CMOS technology in the near future, extensive nanoscale research has been conducted in recent years. The CMOS technologies can function at frequencies of Tera-Hertz and can attain a consistency of 10 devices/cm 2 . However, the current strategy of reducing transistor count while maintaining the same design quality may soon be insufficient to overcome the commercial, architectural, and physical barriers. A novel technology that harnesses the advantages of nanoscale physics will have to replace the MOS transistor. A plethora of cutting-edge technologies, such as spin transistors, resonant tunnelling diodes (RTDs), carbon nanotubes (CNTs), and single electron transistors (SETs), are being investigated as potential replacements for conventional CMOS technology. Because nanotechnology has unique features that increase at such small feature sizes, it opens up new computational possibilities. When creating ultra-deep submicron circuits and getting around CMOSs limitations, quantum-dot Cellular Automata (QCA) is a nanotechnology that can take the place of CMOS. It is created on various scientific facts, including Effective QCA Designs and Their Applications. The proposed XOR Gate are compared with existing designs in terms of number of cells area and clock cycles. The proposed design is purely logical, fast and occupies ultra-less area.