Design and Synthesis of State Transition Graph-Based Sequential Multiplier for Fast Computing Operation

combinational multipliers operate fast but require a significant amount of silicon area. as area is an important consideration, it can be reduced at the expense of performance by scheduling the sub-operations of the multiplier to execute in successive clock cycles. sequential multipliers are compact, require fewer adders, and are amenable to pipelining. the area required by combinational multipliers grows geometrically with the word length, but the area of a sequential multiplier does not increase significantly with the word length, and the number of clock cycles required to complete a multiplication also grows linearly rather than exponentially with the word length. thus, the paper presents the design and synthesis of a sequential multiplier using a state transition graph (stg) controller to optimize performance parameters such as area, power, and delay. the proposed multiplier is designed and synthesized using verilog programming in xilinx ise and the cadence tool. simulation results and rtl diagrams are presented to validate the sequential multiplier operations.