Evaluation of Transmission Line Properties on Si-CMOS Chip by Probe Backside Reflection Method in Millimeter-Wave Frequencies

In this study, we demonstrate the evaluation of effective dielectric constant <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\varepsilon_{\text{eff}})$</tex> and quality factor <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\boldsymbol{Q})$</tex> of transmission lines (TLs) on a Si-CMOS chip using the probe backside reflection (PBR) method in the frequency range up to 220 GHz. The both properties are known to be influenced by distribution of dummy metals around a TL as well as dimensions of a TL. The PBR method is expected to reduce occupied chip area compares to the conventional thru-reflect-line (TRL) method, because the PBR method requires only one co-planar waveguide (CPW) for the evaluation. Three types of the TLs with different cross-sectional structures were designed, and those <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\varepsilon_{\text{eff}}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{Q}$</tex> were evaluated by the PBR method. These results were qualitatively corresponded to the simulation results. Relationship between measurement accuracy and occupied chip area was compared to the conventional TRL method. The PBR method has a possibility to reduce occupied chip area for evaluation of the TL properties.