A Novel Three-Stage CTLE Circuit for 12.5Gbps SerDes

We proposed a novel three-stage CTLE circuit for 12.5Gbps SerDes based on 28nm CMOS process. A cross-coupled negative capacitance structure was adopted to feature more zero poles, the increasing of gain and an adjustable equalization amplitude in single-stage CTLE. As well, a three-stage structure was adopted to feature the gain boost and a favorable eye diagram. At the transmission rate of 12.5Gbps, the proposed circuit demonstrated a single-stage compensation capability of 24.23dB, an output eye-height of 305.38mV, a horizontal jitter control of 0.19UI, and an area of 0.10mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.