Research on Impedance Characteristics of High Speed Differential via

This paper analyzes the factors that affect the impedance of PCIE5.0 differential via on high-speed PCB boards. At the same time, it analyzes the decisive factors that affect the impedance of via when the length of via is long due to thick PCB layers, and proposes optimization solutions. The simulation results show that after via length exceeds 80mil, the impedance caused by parasitic inductance increases significantly. By changing via size and pitch, it was found that increasing via size can significantly reduce via impedance; However, for via in the BGA area, via size and pitch spacing are strictly limited, and changing the antipad cannot eliminate the impedance increase caused by parasitic inductance. Therefore, in the design of high-speed circuit boards, it is necessary to optimize differential via impedance for various influencing factors. At the same time, when designing high-speed boards, try to adjust the routing layer to avoid BGA area and shorten via length as much as possible.