Multiplier Free FIR Filter Design using Array Product Generator and Multiplexer

The FIR filters are widely used in various fields of applications. FPGA implementation of FIR filter has a challenge of complexity and delay. This research study mainly concentrates on the FIR filter design using less resources on the FPGA. The main units in the FIR filter are adders and multipliers, so in order to optimize the overall hardware usage, we proposed a multiplier free design because multipliers are more complex. In general, systems are making their way for less power consumption, less hardware complexity, and less area design. The proposed system is a multiplier free unit; hence, there will be few resources to be utilized as mentioned above. Multiplexer (mux)-based computation sharing approaches and actions, such as memory access operations, distributed arithmetic techniques, and common subexpression sharing, are the operations that are shared commonly. Shift and add operations can be seen extensively in the system. Those are the operations used in the array product generator for the fundamental generation of coefficients, irrespective of multipliers. In contrast to conventional multiplexer (MUX)based approaches, the given structure significantly reduces hardware complexity. The concept of sharing the similar operations for all the filter weights offers potential enhancements to MUX-based filter techniques and multiplierless scenarios, improving the power efficiency of the system and making the circuit design in an easier way. This design becomes ideal for many less power consuming applications.