A 52-Gb/s Low-Power PAM-4 Baud-Rate CDR Using Pattern-Based Phase Detector for Short-Reach Applications

A four-level pulse amplitude modulation (PAM-4) baud-rate clock and data recovery (CDR) is proposed for a power-efficient receiver. The baud-rate CDR reduces the burden of multi-phase clock generation and distribution, thus reducing the power consumption of clocking circuits. A pattern-based phase detector (PBPD) is proposed in the clock recovery path to address the transition density (TD) reduction caused by the baud-rate operation. The PBPD optimizes patterns that provide phase information, increasing TD by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4{\times }$ </tex-math></inline-formula> compared with the conventional baud-rate PD, Mueller-Müller phase detector (MMPD). In addition, the number of comparators required for data recovery is reduced by one per unit interval (UI) by sharing the comparators used for CDR. The CDR prototype fabricated using a 28-nm CMOS is verified using PRBS31 pattern, where a bit error ratio less than 3e-8 is achieved under 5.6-dB channel loss at 0.83-pJ/b energy efficiency while occupying only 0.011 mm2.