Signal Integrity Analysis and Design for HBM3 on Silicon-Based 2.5D Packaging

In this paper, a method is proposed to fast evaluate die to die channel design in 2.5D silicon-based packages to reduce the layout cycle time. To verify that the design obtained through this method can meet the high-speed requirements of High Bandwidth Memory (HBM) Gen3 at data rates of 6.4 Gbps and 7.2 Gbps, interconnect models are extracted using a 3D simulation tool, and time-domain analysis is conducted to confirm the eye diagram performance. This ensures an efficient design process, resulting in designs that can support the signal demands of HBM Gen3.