Design of an Enabling Hysteresis Comparator with Wide Input Voltage Range

Hysteresis comparator is widely used in integrated circuits, and it is a key module in analog circuits such as analog-to-digital converters and power management integrated circuits. This article designs a hysteresis comparator that uses fewer components and achieves dual loop control of hysteresis generated by an externally added inverter circuit. The threshold of the hysteresis voltage can be flexibly designed, enabling the control terminal transmission tube M1 to use different voltage resistant devices to transmit corresponding effective comparison signals to the same phase terminal. The device used in this article can achieve an effective input voltage of up to 1.55V at the EN terminal up to 60V, while using PMOS as the differential input pair tube, with a wide common mode input range of 30mV-1.6V, and dynamic power consumption as low as 1.2 µW. The simulation of hysteresis voltage difference of 55m V was carried out using 0.18 µm BCD process, and the simulation results were consistent with the design expectations.