Asymmetric SiGe BiCMOS SPDT Switch With 210 fs <i>R</i> _ON × <i>C</i> _OFF for 5G Applications

This article presents a compact high-linearity single-pole double-throw (SPDT) switch built using a 0.13-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula>m SiGe BiCMOS technology for Ka-band 5G. The body-floating technique (BFT) based on the deep-n-well (DNW) transistor is used in the asymmetric structure to decrease substrate leakage and improve the power-handling capability in TX mode. Advanced performances have been achieved from the RF switch point of view with 210 fs <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text{ON}} \times {C}_{\text{OFF}}$ </tex-math></inline-formula>. The proposed design achieved a minimum insertion loss (IL) of 0.53/1.33 dB including pad losses, isolation of more than 21/15 dB, and IP1dB of 20/8.5 dBm in TX/RX mode. The measured IIP3 is 34.3/28 dBm at 28 GHz. The active chip area is 0.046 mm2. In contrast to the conventional structure with heterojunction bipolar transistor (HBT) or PIN diodes in SiGe process, the proposed SPDT exhibits good performances with a compact area for modern asymmetric front-end applications.