Design and performance characterisation of 10 nm negative capacitance double gate MOSFET (NCDGMOSFET)

Abstract The major focus on any transistor-level design is to minimize the effects on switching speed and power consumption at smaller dimensions, which are crucial in VLSI design for low power applications. In this work, a double gate MOSFET design is proposed with p+ pocket in the channel region at 10 nm technology node. Further a ferroelectric material HfO 2 FE is also introduced between gate and oxide layer resulting a negative capacitance double gate MOSFET (NCDGMOSFET). Ferroelectric material shows negative capacitance that limits the subthreshold slope with dimension scaling. Increased gate control and high switching speed in NCDGMOSFET with lightly doped n-channel, is a promising transistor option for low-power high performance IC design. The proposed device design is characterised with different pocket dimensions for gate and drain voltage ranges from 0 V to 1.5 V. The contact resistance of drain and source is also varied to observe device ON/OFF performances. The electrostatic behaviour of the device is also analysed via observation of electric field and potential variations at different bias conditions. Adding a p+ pocket in the NCDGMOSFET structure further enhances the performance by modifying the channel properties with subthreshold slope and DIBL vales of 76 mV decade −1 and 36 mV/V respectively. This modification also leads to improved barrier to subthreshold conduction during the I off state of the transistor, while minimally impacting the I on state. The proposed device design and performance analysis are conducted through TCAD 2D/3D device simulation software by Cogenda.