Systematic Offset Voltage Reduction Methods Using Half-Circuit of Input Stage in the Two-Stage CMOS Operational Amplifiers and Comparators

In this study, we propose the systematic offset voltage reduction method considering the channel length modulation effect for the two-stage CMOS operational amplifiers (Op-Amps) and comparators. The proposed method employs the half-circuit of the input stage in two-stage Op-Amps as the output stage. Using the proposed method, each terminal voltage of the MOS transistors in the input and output stages is aligned, and the channel length modulation effect can be ignored. To generalize the proposed method, we applied the proposed method to Op-Amps with the cascode active load and differential difference amplifier. The systematic offset voltage was evaluated and compared by simulation using HSPICE with TSMC 0.18 μm model parameters. Consequently, we confirmed that the proposed method can reduce the systematic offset voltage by 95% or more.