High Performance Approximate Multiplier using reversible logic gates

Reversible logic has previously been shown to cause higher power consumption and a significant amount of dissipated energy because of information loss in standard design methods. This project describes the approximate multiplier using Reversible logic gates. In this design, the reversible logic gates replace the half adder and full adders in the multiplier. It uses two RG(Reversible Gate) in place of single reversible gate. So that it reduces the garbage value produced, which helps to decrease the overall delay and power consumption. The proposed Approximate Multiplier uses the product’s least significant half as a constant compensation term and the remaining half is precisely calculated. This can be a effective alternative for exact multipliers in practical error-resilient applications and Digital Image Processing.