Visual Simulation of a Digital Hardware Model

Visual simulation in circuit design involves creating a software application that provides a dynamic visual representation of a digital system modeled with Hardware Description Languages (HDLs). This allows users to gain a deeper understanding of the system's behavior by observing the simulation in real-time. Additionally, the simulation data facilitates easier identification and correction of malfunctions in digital circuits models. This report explores the capabilities of the Visual Debug (VIZ) feature in the Makerchip IDE for creating a visual simulation of a stack-based calculator model. This model is specifically designed for online learning in digital hardware design courses offered by the Computer Systems and Technologies department at the Technical University of Gabrovo.