Power-Optimized Field-Programmable Gate Array Implementation of Neural Activation Functions Using Continued Fractions for AI/ML Workloads

The increasing demand for energy-efficient hardware platforms to support artificial intelligence (AI) and machine learning (ML) algorithms in edge computing has driven the adoption of system-on-chip (SoC) architectures. Implementing neural network (NN) activation functions, such as the hyperbolic tangent (tanh), on hardware presents challenges due to computational complexity, high resource requirements, and power consumption. This paper aims to optimize the hardware implementation of the tanh function using continued fraction and polynomial approximations to minimize resource consumption and power usage while preserving computational accuracy. Five models of the tanh function, including continued fraction and quadratic approximations, were implemented on Intel field-programmable gate arrays (FPGAs) using VHDL and Intel’s ALTFP toolbox, with 32-bit floating-point outputs validated against MATLAB’s 64-bit floating-point results. Detailed analyses of resource utilization, power optimization, clock latency, and bit-level accuracy were conducted, focusing on minimizing logic elements and digital signal processing (DSP) blocks while achieving high precision and low power consumption. The most optimized model was further integrated into a four-input, two-output recurrent neural network (RNN) structure to assess real-time performance. Experimental results demonstrate that the continued fraction-based models significantly reduce resource usage, computation time, and power consumption, enhancing FPGA performance for AI/ML applications in resource-constrained and power-sensitive environments.