FRAM Array: A Device and Circuit Interaction Study at Advanced Technology Nodes

To reveal the inner links between the circuits’ performance and the capacitor’s behavior of the ferroelectric random access memory (FRAM), the Landau-Khalatnikov (L-K) model and an EDA tool simulation-based devices-array co-analysis method are developed in this work. A controlled source-based equivalent circuit was proposed to represent the L-K model, and its model parameters extracting method is proposed, which only requires the measurement of hysteresis loop via different rising speeds. The Elmore delay model is utilized to describe the equivalent circuit modeling of the array interconnects in FRAM. Based on the developed method, by varying the parameters of the ferroelectric capacitors, we can evaluate the FRAM’s performance, including the sense margin and read latency. Overall, the developed method links the FRAM’s cell characteristics to the circuit’s performance, providing an efficient way for FRAM’s study at advanced nodes (<1Z nm) and providing valuable insights into its circuit design and optimization. This work provides a simulation method and guideline for device and circuit design and optimization of FRAM arrays from a circuit and device interaction perspective.