A Systematic Study of Charge-Trapping Phenomenon in FeFET on FDSOI via Low-Frequency Noise Spectroscopy

The presence of charge trapping dynamics in general ferroelectric-gate field effect transistors (FeFETs) is significant in the memory window (MW) modulation and optimization. To comprehend underlying mechanisms of this phenomenon, the low-frequency (i.e., 1/f noise) measurements in a wide range of programming/erasing voltages are conducted for HfO2-based FeFETs on FDSOI. When applying the small DC sweeping, a counterclockwise hysteresis is obviously observed, resulting from the charge trapping dynamics induced carrier density fluctuations near interfaces between DE-layer and FE-layer. By increasing the voltage amplitude, a transition from failure, to partial and then to a complete memristive operation is observed. It is determined by combination of gate dielectric trap density, ferroelectric polarization and bias temperature instability. Combining experimental data and LFN-based models, the corresponding defect density distributions inside the stacked gate oxides are extracted to explain the complex current hysteresis transition and threshold voltage shift behaviors.