The Influence and Optimization Constraints of SiC Power Module Layout on High-Frequency Conducted CM Current During Switching Transients

The penetration rate of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small>s is gradually increasing due to their excellent electrical and thermal characteristics. However, the wide-bandgap devices exhibit faster di/dt, dv/dt and are more sensitive to parasitic inductances of power module during switching transients. Meanwhile, the influence of parasitic inductances on the propagation path of electromagnetic interference cannot be ignored either. The coupling between the switching transient waveforms and the propagation paths is formed through parasitic inductances. This article elucidates the impact of parasitic inductances and capacitances of power modules at different positions on common mode (CM) current during switching transients and provide constraints for the optimal range of parasitic parameters by establishing a conducted time-domain CM mathematical model considering power modules's parasitic parameters. The switching waveforms are divided into CM noise sources and differential mode (DM) noise sources. So the CM current is not only related to the CM noise source, but also to the DM noise source due to the asymmetric parasitic parameters of the power module. Based on the analysis, this article can identify the impact of parasitic parameters at different positions of power modules on CM current at different switching stages and guide the selection and redesign of the commercial power modules to reduce CM current and switching losses based on the switching characteristics. In the experiment, the double pulse test with power module BSM120D12P2C005 is established, and the influence of different layouts of power modules on CM current is verified and compared.