Design and Implementation of a High-Reliability Min-Max Algorithm for LDPC Decoder on FPGA

LDPC codes improve error correction performance in soft-decision decoding by using the reliability of the received signal, offering greater accuracy than hard-decision decoding. The High Reliability Min-Max Algorithm leverages this advantage by using LLR to reduce computational complexity while improving decoding accuracy. The (837, 726) Min-Max code maintains performance similar to LDPC while being more efficient, reducing hardware resource usage and power consumption. Compared to the (4191, 3602) binary LDPC code, it offers better transmission efficiency. This paper presents the simulation results for a (512, 256) code, and the hardware implementation, using pipeline and parallel structures, highlights the high error correction capability of the proposed Min-Max code. This structure combines the error correction strengths of QC-LDPC with the simplicity of binary LDPC's hardware implementation. The proposed algorithm demonstrates similar error correction performance to LDPC codes but achieves lower complexity and higher transmission efficiency.<br/> Future research will focus on comparing the performance through ASIC implementation to further assess its effectiveness in practical systems. This comparison will offer insights into how the proposed Min-Max code can be implemented for real-world applications requiring efficient and reliable error correction performance.