An Impedance Measurement System-on-Chip for Flow Cytometry with On-Chip Size Classification

This paper presents an impedance measurement system-on-chip (SoC) for flow cytometry (i.e. cell counting) applications. A source-differential lock-in architecture is used, including a high-gain TIA, mixers and a low-pass filter. At the back-end, the SoC includes digital feature extraction and linear classification for real-time cell size determination. A measured prototype IC achieves $156 \mathrm{fA} / \sqrt{H z}$ noise floor and 3.2 pArms input-referred noise from $1-1 \mathrm{kHz}$. Following offline training, the SoC demonstrates classification of $4.5 \mu \mathrm{~m}$ and $6 \mu \mathrm{~m}$ beads with a prediction accuracy of 86.16% using the on-chip classifier.