A Fully Integreated Current-Mode LDO Using PSRC and APSR Technique With -71.8 dB PSRR at 6.78 MHz for Implantable Medical Device

This paper presents a fully integrated capacitor-less high PSRR LDO based on current-mode topology. A power supply ripple cancellation technique (PSRC) is proposed to improve the PSRR at high frequency. The PSRC is based on the flipped voltage follower (FVF) and the super source follower structure (SSF) is added to improve the stability of proposed LDO. The small signal of the PSRC technique is set up and the PSRR at low frequency is not affected in proposed LDO. In addition, an adjustable PSRR technique is achieved. The PSRR at the range from 100 kHz to 10 MHz can be greatly improved at a specific frequency by adjusting the value of the compensation resistance according to the working frequency of specific applications. The proposed LDO is designed in a $0.18 \mu \mathrm{~m}$ CMOS process, which achieves the PSRR of -79 dB at DC and -71.8 dB at 6.78 MHz. Moreover, the PSRR is enhanced by 30 dB at 126 MHz.